- Title
- Mitigation of single event upsets in a XILINX ARTIX-7 field programmable gate array
- Creator
- Omolo, Joshua
- Subject
- Field programmable gate arrays -- Design and construction Prototypes, Engineering
- Date Issued
- 2018
- Date
- 2018
- Type
- Thesis
- Type
- Masters
- Type
- MEng
- Identifier
- http://hdl.handle.net/10948/22310
- Identifier
- vital:29942
- Description
- Field programmable gate arrays are increasingly being used in harsh environments like space where high energy particles from radiation affect the integrity of the data. Before deployment of satellites in space, characterisation and consequently mitigation of radiation effects is necessary to avoid failure. By irradiating a digital microelectronic device, using accelerated energetic particles, it is possible to predict the likelihood of an event effect happening. Such irradiation tests can only be done at a particle accelerator facility such as iThemba LABS in Cape Town. It is the one of the few particle accelerators in the southern hemisphere and offers the capacity to perform these event effect characterisation tests. Triple Modular Redundancy (TMR) is a commonly used mitigation technique in microelectronics. Although effective, it has the downside of increased resource area. A DMR-Filter combination mitigation technique was developed at the Nelson Mandela University. It uses fewer resources than TMR and it is envisaged to significantly reduce event upsets in a FPGA. This research project seeks to investigate the effectiveness of the DMR-Filter combination mitigation technique in reducing the likelihood of event upsets occurring in Xilinx’s Artix-7 FPGA when exposed to highly accelerated particles, similar to those in space.
- Format
- xiii, 97 leaves
- Format
- Publisher
- Nelson Mandela University
- Publisher
- Faculty of Engineering, the Built Environment and Information Technology
- Language
- English
- Rights
- Nelson Mandela University
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| Thumbnail | File | Description | Size | Format | |||
|---|---|---|---|---|---|---|---|
| View Details Download | SOURCE1 | Mitigation of single event upsets in a XILINX ARTIX-7 field programmable gate array | 4 MB | Adobe Acrobat PDF | View Details Download |